This disclosure relates generally to semiconductor devices and more particularly, to pillar structures having a non-planar surface for semiconductor devices.
The past few decades have seen many shifts in electronics and semiconductor packaging that have impacted the entire semiconductor industry. The introduction of surface-mount technology (SMT) and ball grid array (BGA) packages were generally important steps for high-throughput assembly of a wide variety of integrated circuit (IC) devices, while at the same time allowing for reduction of the pad pitch on the printed circuit board. Conventionally packaged ICs have a structure basically interconnected by fine gold wire between metal pads on the die and electrodes spreading out of molded resin packages. Dual Inline Package (DIP) or Quad Flat Package (QFP) are fundamental structures of current IC packaging. However, increased pin count peripherally designed and arranged around the package typically results in too short of a pitch of lead wire, yielding limitations in board mounting of the packaged chip.
Chip-scale or chip-size packaging (CSP) and BGA packages are just some of the solutions that enable dense electrode arrangement without greatly increasing the package size. Some CSP techniques may provide the additional advantage of allowing for wafer packaging on a chip-size scale. CSP typically results in packages within 1.2 times the die size, which greatly reduces the potential size of devices made with the CSP material.
Some CSP or BGA packages rely on bumps of solder to provide an electrical connection between contacts on the die and contacts on a substrate, such as a packaging substrate, a printed circuit board (PCB), another die/wafer, or the like. Other CSP or BGA packages utilize a solder ball or bump placed onto a bump electrode or pillar, relying on the soldered joint for structural integrity. The different layers making up the interconnection typically have different coefficients of thermal expansion (CTEs). As a result, a relatively large stress derived from this difference is exhibited on the joint between the post and the bump electrode, which often causes cracks to form in the bonding area between the bump electrode/pillar and the solder ball or bump.